`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    21:07:17 05/22/2014 
// Design Name: 
// Module Name:    stage 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
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module stage (



		// interface to the video logic
	input 		[9:0]	vid_row,		// video logic row address
						vid_col,		// video logic column address
	output		[1:0]	vid_pixel_out,	// pixel (location) value

	// interface to the system
	input				clk,			// system clock
						reset			// system reset
);


		
		
		
reg 	[13:0] 	vid_addr;	// dual port RAM addresses for 
										// external world emulator and video logic
											
// Instantiate the world map ROM (generated by Xilinx Core Gnerator


Stage_RAM RAM(
  .clka(clk),
  .wea(1'b0),
  .addra(14'b0),
  .dina(2'b0),
  .clkb(clk),
  .rstb(reset),
  .addrb(vid_addr),
  .doutb(vid_pixel_out)
 );
	
	
// implement the address latches
always @(posedge clk) begin
	vid_addr <= {vid_row[6:0], vid_col[6:0]};
end
	
endmodule
